SNNs are event-driven — neurons fire sparsely and asynchronously. Each spike triggers a small amount of computation. This pattern doesn't fill GPU warps efficiently. SIMD lanes sit idle waiting for spikes that may or may not arrive. A CPU core with low latency between dependent instructions is a better match.
Each timestep depends on the membrane potentials from the previous timestep. This is a genuine data dependency chain — not something you can parallelize away. Multi-threading adds synchronization overhead without reducing the critical path. The bottleneck is clock frequency, not core count.
Deployment target is ARM mobile. Pre-training on the same ISA avoids floating-point divergence between architectures. With SNNs, small numerical differences compound across thousands of timesteps — bit-identical results matter.